The present invention relates to carrier packages for integrated circuit chips, and particularly relates to such carrier packages having a grid array of input/output pins which may be interconnected to similar carrier packages.
With the development of high performance computer logic integrated circuit chips having multiple input/output terminals, carrier packages have been developed which use a planar method of interconnection between the input/output terminals of multiple integrated circuit chips. Such packages require large printed circuit board surface areas and long signal conductors, resulting in excessive signal delay and degraded performance. Costly multilayer printed circuit boards have also been developed in order to decrease the surface area and reduce the signal distance for interconnecting multiple integrated circuit chips.
U.S. Pat. No. 3,676,748 to Kobayshi et al. for "Frame Structure for Electronic Circuits", issued July 11, 1972, discloses a frame for holding electronic circuits which may be stacked vertically as shown in FIG. 6. The disclosed frame provides for planar terminal connector members 12 and 14.
U.S. Pat. No. 3,718,750 to Sayers for "Electrical Connector", issued Feb. 27, 1973, discloses an electrical connector having female terminals for connection with electrical leads from printed circuit boards, and a male terminal for connection with the female terminals arranged in a stack.
U.S. Pat. No. 4,137,559 to Reuting for "Socket Assembly", issued Jan. 30, 1979, discloses a plurality of frames which may be stacked in a tube. Each frame may contain a printed circuit board or a large scale integrated circuit chip. The lower frame may be equipped with contact pins which extend from the bottom of that particular socket section.
U.S. Pat. No. 4,514,784 to Williams et al. for "Interconnected Multiple Circuit Module", issued Apr. 30, 1985, discloses an arrangement having connector assemblies for interconnecting two circuit modules. Each circuit module has cooling plates through which interconnecting pins pass for connection into the connector assemblies. The cooling plates have clearance holes through which the interconnecting pins pass so that there is no electrical contact between the pins and the cooling plates.
U.S. Pat. No. 4,620,632 to Alemanni for "Carriers For Pin Grid Array", issued Nov. 4, 1986, discloses an integrated circuit chip carrier having a body with a plurality of pins projecting from at least one face of the body for plugging into a printed circuit board.